The Acer Aspire 5935, built on the Compal LA-5011P (JIWA3/JIWA4) motherboard, represents the pinnacle of the Intel Centrino 2 era. Featuring the Penryn-class Core 2 Duo processors paired with the Intel PM45/GM45 Northbridge and ICH9M Southbridge, this platform is a classic example of Compal's multi-rail architecture. For repair technicians, the LA-5011P is a robust board, but it often suffers from thermal fatigue in the discrete GPU section and aging electrolytic filtering in the VCORE circuit. This guide provides deep-dive technical insights into the power distribution and signal sequencing for successful chip-level recovery.
Board Architecture & Technical Specifications
| Feature | Specification / Component |
|---|---|
| Motherboard Model / ODM | Compal LA-5011P (JIWA3/JIWA4) |
| CPU Architecture | Intel Socket P (Penryn / Core 2 Duo) |
| Chipset | Intel PM45/GM45 Northbridge + ICH9M Southbridge |
| Super I/O (EC) | ENE KB926QF D3 |
| Charging IC | Intersil ISL6251AHRZ |
| Main Voltage Rails | +3VALW (PL4), +5VALW (PL5), +1.05VSP (PL10), +VCC_CORE (PL11/PL12) |
Real-World Motherboard Diagnostic Procedures
1) DC-IN Protection & Charging Logic Analysis
On the LA-5011P, the 19V adapter voltage enters through the DC jack and is managed by the ISL6251 (PU1). The first and second protection MOSFETs (typically PQ1 and PQ2) must be biased correctly at their gates to allow +19VB to propagate to the rest of the board. If you find 19V at the drain of PQ1 but 0V at the source of PQ2, check the ACIN signal (Pin 2) and DCIN (Pin 24) of PU1. A common failure point is the current sensing resistor PR3; if it drifts in value, the ISL6251 may shut down the input stage due to perceived overcurrent. Ensure the gate drive voltage is approximately 25V (generated via internal charge pump) to fully saturate the N-channel MOSFETs.
2) Standby Rail Generation (+3VALW / +5VALW)
The always-on rails are managed by the TPS51125 (PU4) or a compatible PWM controller. This IC generates +3VALW (at PL4) and +5VALW (at PL5). Before these switching rails appear, the IC must output its internal LDO voltages: VREG3 (Pin 8) and VREG5 (Pin 17). If these are missing, PU4 is likely defective or there is a short on the LDO lines (often the EC or the Southbridge standby section). In this era of Compal boards, a resistance lower than 100 ohms on PL4 usually indicates a shorted ENE KB926 Super I/O chip. Always verify the EN0 (Enable) signal from the power circuitry before replacing the PWM controller.
3) Power-On Sequence & ICH9M Wake-up
The transition from Standby (S5) to Working (S0) state on the LA-5011P follows a strict Compal sequence. When the power button is pressed, the EC (KB926) sends KBC_PWRBTN# to the ICH9M Southbridge. The Southbridge must then respond by releasing PM_SLP_S4# and PM_SLP_S3#. These signals trigger the high-side MOSFETs for the "VS" (switched) rails. If the board triggers but immediately shuts down, check the +VCC_CORE at PL11/PL12. This board uses an ISL6262 (PU10) for CPU power. Ensure the VR_ON signal is present. If the CPU voltage is present but there is no display, the ICH9M 32.768kHz crystal (Y2) or a corrupted BIOS dump (U16/U25) are the primary suspects.
Download Schematic & Boardview Files
Direct download link. Verified schematic / boardview archive for JIWA3/JIWA4.
Professional Repair Assistance
Explore our technician resources:
- 🛠️ Diagnose No-Power & Short-Circuit faults step-by-step: Interactive Laptop Diagnostic Lab
- 🛒 Original Replacement Motherboards & IC Components: Official Spare Parts Mega Store
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