Acer Aspire 9800 9810 9920 (Compal Cheela) Schematic & Boardview: Chip-Level Repair Guide

The Acer Aspire 9800, 9810, and 9920 series represent the pinnacle of the "Desktop Replacement" era. Built on the Compal Cheela architecture, these massive 20-inch machines utilize the Intel Core 2 Duo platform paired with the ICH8M Southbridge and dedicated MXM graphics. For a senior chip-level engineer, the Cheela board is a classic example of Compal's multi-rail power distribution logic, requiring precise timing for the secondary rails to initialize the MXM GPU module and the high-resolution LCD panel.

Board Architecture & Technical Specifications

Feature	Specification
Motherboard Model / ODM	Compal Cheela (LA-3121P / LA-3551P Variant)
Target Laptop Series	Acer Aspire 9800, 9810, 9920 (20" DTR)
Chipset / CPU Architecture	Intel 945PM/965PM + ICH7M/ICH8M (Socket P/M)
Super I/O (EC/KBC)	ENE KB926QF / KB910
Key Voltage Rails	+3VALW (PL5), +5VALW (PL4), +1.8V (PL10), +VCC_CORE (PL11)

Real-World Motherboard Diagnostic Procedures

1) Input Power Stage & DC-IN Protection Circuit

The Cheela board utilizes the ISL6251 (PU1) charging controller. When the adapter is connected, 19V must pass through the dual P-Channel MOSFETs PQ1 and PQ2.

• Diagnostic Step: Measure voltage at the current sense resistor PR3. If 0V, check the gate voltage of PQ1 (pin 4). This gate is driven by the ISL6251's ACDRV signal.
• Common Failure: If ACIN (pin 2) on PU1 is below 3.2V, the IC will not open the entry MOSFETs. Verify the voltage divider PR8 and PR12 for drift.

2) Standby Supply & LDO Generation (+3VALW/+5VALW)

The Always-On rails are generated by PU4 (MAX8744). This IC must produce the +5V LDO (VREG5) before the switching rails can start.

• Diagnostic Step: Check PL5 for +3VALW and PL4 for +5VALW. If missing, verify that EN_3V_5V (from the ENE KBC) is high (~3.3V).
• Legacy Tip: On these older boards, the electrolytic decoupling capacitors near the coils often leak or lose ESR. If the 3V/5V rails show ripple on an oscilloscope, replace the filter caps immediately even if they look physically intact.

3) Power-On Sequence & Signal State Tracking

For the Cheela to transition from S5 (Standby) to S0 (Running), the Power Management handshake must be complete:

• Step A: Ensure RTC_RST# is 3.3V at the Southbridge. If the CMOS battery is below 2.5V, these older ICH8M chipsets may fail to trigger the power-up sequence.
• Step B: Trace the PWR_SW# signal to Pin 32 of the KB926 KBC. When the power button is pressed, this pin must toggle. In response, the KBC should release PM_SLP_S3# and PM_SLP_S4#.
• Step C: If the laptop turns on but has no display, check the MXM slot power. The +VCC_GFX rail on the MXM card is a frequent failure point due to thermal stress on the GPU core.

Download Schematic & Boardview Files

📥 Download ACER-ASPIRE-9800-9810-9920 CHEELA REV.000 Schematic / Boardview

Direct download link. Verified schematic / boardview archive.

Professional Repair Assistance

Explore our technician resources:

• 🛠️ Diagnose No-Power & Short-Circuit faults step-by-step: Interactive Laptop Diagnostic Lab
• 🛒 Original Replacement Motherboards & IC Components: Official Spare Parts Mega Store