Showing posts with label Cloudbook. Show all posts
Showing posts with label Cloudbook. Show all posts

Sunday, November 8, 2026

Acer Aspire One Cloudbook 11 AO1-131 14 AO1-431 (Wistron Caltech Oxford MB-AX1) Schematic & Boardview - Chip-Level Diagnostic Guide

The Acer Aspire One Cloudbook series (AO1-131 and AO1-431) represents a shift toward ultra-portable, low-power computing, built around the Intel Braswell SoC architecture. These machines utilize the Wistron Caltech/Oxford (MB-AX1) motherboard, a highly integrated design where the CPU, RAM, and eMMC storage are soldered directly to the PCB. For repair technicians, this integration means that traditional component swaps (like HDD or RAM) are impossible, making chip-level diagnostics on the power delivery network (PDN) and signal sequencing the only viable path for restoration.

Board Architecture & Technical Specifications

FeatureSpecification
Motherboard Model / ODMWistron Caltech / Oxford MB-AX1
Platform ArchitectureIntel Braswell (Celeron N3050 / N3060)
Super I/O (EC) ControllerNuvoton NPCE985PB1DX
Charging Controller ICTI BQ24735RGRR
Key Voltage RailsDCBATOUT, 3D3V_AUX_S5, 5V_AUX_S5, 1D0V_S0

Real-World Motherboard Diagnostic Procedures

1. DC-IN Isolation & DCBATOUT Verification

In the Wistron Caltech architecture, the primary 19V rail is labeled DCBATOUT. If the laptop is completely dead, start by probing the current sense resistor R0201 (typically located near the BQ24735 charging IC). If you do not measure 19V here, check the gate voltage of the two input P-Channel MOSFETs. The BQ24735 must pull the ACDRV pin to approximately 25V (6V above the adapter voltage) to open these N-channel gates. If ACDRV is missing, verify the REGN (6V LDO) and ACDET (approx. 2.6V) pins on the charging IC. A common failure point in this model is a shorted ceramic decoupling capacitor on the DCBATOUT line, which triggers the adapter's OCP (Over Current Protection).

2. Standby Rail Generation (3.3V/5V Always-On)

The Caltech MB-AX1 utilizes a dual buck converter (often the TPS51225) to generate the 3D3V_AUX_S5 and 5V_AUX_S5 rails. These rails are critical as they power the Super I/O and the BIOS chip. Before replacing the PWM IC, measure the resistance to ground on coils L4501 and L4502. On this Braswell platform, a low resistance (under 50 ohms) on the 3.3V rail often indicates a punctured SoC (Intel Celeron), which is a common result of a cheap third-party charger failure. If resistances are normal (k-ohms range) but voltages are missing, check the EN2 and EN1 signals coming from the EC.

3. Power-On Sequence & Signal State Tracking

If the standby rails are present but the unit fails to trigger, monitor the KBC_PWRBTN# signal at the NPCE985 Super I/O. When the power button is pressed, this signal should drop from 3.3V to 0V and back. The EC should then release SIO_PWRBTN# to the SoC. If the SoC is healthy and receives its RTCRST# and SRTCRST# signals (check the 3V CMOS battery), it should respond by pulling PM_SLP_S4# and PM_SLP_S3# high. In these Cloudbooks, a corrupt BIOS/ME Region is a frequent cause for the sequence to hang at the S3 state. Always perform a clean ME region BIOS dump before attempting hardware replacement on the SoC.

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