The Acer Chromebook 11 CB3-131, built on the Quanta ZHS (DA0ZHSMB6E0) motherboard architecture, is a staple of the educational laptop market. This fanless design utilizes the Intel Bay Trail-M SoC (System on Chip), which integrates the CPU, GPU, and Southbridge into a single package. For the chip-level repair engineer, this board presents unique challenges, particularly regarding the power management of its soldered LPDDR3 RAM and the specific power-up sequence required by ChromeOS firmware. In this guide, we break down the Quanta-specific rail nomenclature and common failure points found in the ZHS Revision 1A platform.
Board Architecture & Technical Specifications
| Feature | Technical Specification |
|---|---|
| Motherboard Model / ODM | Quanta ZHS (DA0ZHSMB6E0) REV 1A |
| Target Laptop Series | Acer Chromebook 11 CB3-131 / Cloudbook |
| Chipset / CPU Architecture | Intel Bay Trail-M (Celeron N2840) |
| Super I/O (EC/KBC) | ENE KB9022Q / KB9012 |
| Key Voltage Rails | +3VPCU (PL8), +5VPCU (PL9), +1.35V_DDR (PL10), +VCC_CORE (PL11) |
Real-World Motherboard Diagnostic Procedures
1) Input Power Stage & BQ24715 Charging Logic
On the Quanta ZHS platform, the DC-IN voltage (VA) enters through the jack and must pass through two N-channel isolation MOSFETs (typically PQ25 and PQ26). The gate control is managed by the BQ24715 Charging IC. If the board is dead with 0.00A draw:
- Check ACDET (Pin 6): It should be approximately 2.6V (derived from VA via a resistor divider). If this is missing, the IC won't enable the ACDRV (Pin 4).
- Verify REGN (Pin 16): This 6V internal LDO must be present for the IC to function.
- Measure the current sense resistor PR129. A common fault involves the high-side ceramic capacitors shorting to ground, causing the BQ24715 to enter protection mode.
2) Standby & Secondary Rails (+3VPCU / +5VPCU)
The Quanta ZHS uses a dedicated PWM controller (often the TPS51225) to generate the Always-On rails. In Quanta terminology, these are +3VPCU and +5VPCU. These rails must be present before the power button is pressed.
- Coil Resistance: Measure the resistance to ground on PL8 (+3VPCU) and PL9 (+5VPCU). If PL8 shows less than 100 ohms, the SoC or the ENE EC chip may be partially shorted.
- Enable Signals: The EC sends S5_ON to enable the secondary switching regulators. If +3VPCU is present but +3V/+5V (S5 state) are missing, verify the EC's power-on sequence.
3) Power-On Sequence & ChromeOS Reset Logic
Unlike Windows-based laptops, this Chromebook relies on specific EC-to-SoC handshakes. Tracking the NBSWON# signal at the EC (Pin 114) is critical. When the power button is pressed, NBSWON# should drop to 0V and pull back to 3.3V.
- RSMRST#: Ensure the EC releases RSMRST# (3.3V) to the SoC. Without this, the Bay Trail chip will never exit the reset state.
- BIOS/Firmware: The SPI Flash (U11) contains the coreboot/ChromeOS firmware. Corrupt firmware often leads to a "Blue LED on, no display" symptom. Always backup the original dump before flashing a clean ME/TXE region image.
- Clocking: Verify the 32.768kHz crystal (Y3) oscillation using an oscilloscope; without this heartbeat, the PMU inside the SoC will not initiate the S3 power state.
Download Schematic & Boardview Files
Direct download link. Verified schematic / boardview archive.
Professional Repair Assistance
Explore our technician resources:
- 🛠️ Diagnose No-Power & Short-Circuit faults step-by-step: Interactive Laptop Diagnostic Lab
- 🛒 Original Replacement Motherboards & IC Components: Official Spare Parts Mega Store
